The present invention relates to a clock distribution system for a multi-input system.
For example, a multi-bit latch includes individual latch stages for each bit of a multi-bit input signal. Typically, each latch stage receives a true and a complement input clock signal in common. Each latch stage outputs a corresponding data signal according to clock states of the input clocks.
Transistors within latch circuits are susceptible to gate-to-drain feed-through capacitance, which creates an interdependency between the input clock signals and a corresponding input bit for a latch stage. Transitions of the input clock signals vary based on the state of the input bit which can cause errors in transitions of output data signals generated by the latch stage. Since each latch stage shares the true and complement input clock signals in common, the errors produced by feed-through capacitance for each bit-wise latch propagates across all latch stages for the multi-bit latch. This compounds the output data errors for the multi-bit latch.
Current solutions for overcoming feed-through capacitance errors often involve providing cascaded latch stages for each bit of the multi-bit input signal. However, such solutions increase the silicon area and power consumption for multi-bit latches. As the bit width of a multi-bit latch increases, the increase in silicon area and power consumption scale in kind.
Accordingly, there is a need in the art for a more efficient clock distribution system that minimizes feed-through capacitance errors for a multi-bit latch.